Tobias LudwigTU Kaiserslautern
Shift-left with formal: Avoid expensive re-spins in digital IC design
Complexity of hardware designs is ever on the rise and with it the burden of design verification. While there have been significant improvements in design and verification methodologies, these have been merely sufficient to offset the increase in design complexity. In 2020, 68% of ASIC projects finished behind schedule, with only 32% achieving first-silicon success, i.e., over two thirds required at least one re-spin. Nearly 50% of these were caused by logical or functional bugs, a number that has remained virtually unchanged since the early 2000’s.
To resolve these issues, we present VERITAS, a tool flow enabling a shift-left of not only SW, but also of HW verification from RTL to ESL. By automatically generating a formal Verification IP (VIP), the entry hurdle to formal methods is considerably reduced, opening them to a wider audience, which effectively ‘democratizes’ them. The VIP is used to find functional bugs (or flaws) very early in the design cycle and is very efficient in finding control related bugs that are hard to detect with most simulation-based approaches.
The expected benefits of this approach is - to name only a few - better design quality, improved system safety, enhanced cybersecurity and a faster time to market.